1 | /* $NetBSD: mii.h,v 1.20 2016/10/28 05:47:16 msaitoh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (c) 1997 Manuel Bouyer. All rights reserved. |
5 | * |
6 | * Modification to match BSD/OS 3.0 MII interface by Jason R. Thorpe, |
7 | * Numerical Aerospace Simulation Facility, NASA Ames Research Center. |
8 | * |
9 | * Redistribution and use in source and binary forms, with or without |
10 | * modification, are permitted provided that the following conditions |
11 | * are met: |
12 | * 1. Redistributions of source code must retain the above copyright |
13 | * notice, this list of conditions and the following disclaimer. |
14 | * 2. Redistributions in binary form must reproduce the above copyright |
15 | * notice, this list of conditions and the following disclaimer in the |
16 | * documentation and/or other materials provided with the distribution. |
17 | * |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
28 | */ |
29 | |
30 | #ifndef _DEV_MII_MII_H_ |
31 | #define _DEV_MII_MII_H_ |
32 | |
33 | /* |
34 | * Registers common to all PHYs. |
35 | */ |
36 | |
37 | #define MII_NPHY 32 /* max # of PHYs per MII */ |
38 | #define MII_ADDRBITS 5 /* Register address bits (0x00..0x1f) */ |
39 | #define MII_ADDRMASK 0x1f /* Address mask */ |
40 | |
41 | /* |
42 | * MII commands, used if a device must drive the MII lines |
43 | * manually. |
44 | */ |
45 | #define MII_COMMAND_START 0x01 |
46 | #define MII_COMMAND_READ 0x02 |
47 | #define MII_COMMAND_WRITE 0x01 |
48 | #define MII_COMMAND_ACK 0x02 |
49 | |
50 | #define MII_BMCR 0x00 /* Basic mode control register (rw) */ |
51 | #define BMCR_RESET 0x8000 /* reset */ |
52 | #define BMCR_LOOP 0x4000 /* loopback */ |
53 | #define BMCR_SPEED0 0x2000 /* speed selection (LSB) */ |
54 | #define BMCR_AUTOEN 0x1000 /* autonegotiation enable */ |
55 | #define BMCR_PDOWN 0x0800 /* power down */ |
56 | #define BMCR_ISO 0x0400 /* isolate */ |
57 | #define BMCR_STARTNEG 0x0200 /* restart autonegotiation */ |
58 | #define BMCR_FDX 0x0100 /* Set duplex mode */ |
59 | #define BMCR_CTEST 0x0080 /* collision test */ |
60 | #define BMCR_SPEED1 0x0040 /* speed selection (MSB) */ |
61 | |
62 | #define BMCR_S10 0x0000 /* 10 Mb/s */ |
63 | #define BMCR_S100 BMCR_SPEED0 /* 100 Mb/s */ |
64 | #define BMCR_S1000 BMCR_SPEED1 /* 1000 Mb/s */ |
65 | |
66 | #define BMCR_SPEED(x) ((x) & (BMCR_SPEED0|BMCR_SPEED1)) |
67 | |
68 | #define MII_BMSR 0x01 /* Basic mode status register (ro) */ |
69 | #define BMSR_100T4 0x8000 /* 100 base T4 capable */ |
70 | #define BMSR_100TXFDX 0x4000 /* 100 base Tx full duplex capable */ |
71 | #define BMSR_100TXHDX 0x2000 /* 100 base Tx half duplex capable */ |
72 | #define BMSR_10TFDX 0x1000 /* 10 base T full duplex capable */ |
73 | #define BMSR_10THDX 0x0800 /* 10 base T half duplex capable */ |
74 | #define BMSR_100T2FDX 0x0400 /* 100 base T2 full duplex capable */ |
75 | #define BMSR_100T2HDX 0x0200 /* 100 base T2 half duplex capable */ |
76 | #define BMSR_EXTSTAT 0x0100 /* Extended status in register 15 */ |
77 | #define BMSR_MFPS 0x0040 /* MII Frame Preamble Suppression */ |
78 | #define BMSR_ACOMP 0x0020 /* Autonegotiation complete */ |
79 | #define BMSR_RFAULT 0x0010 /* Link partner fault */ |
80 | #define BMSR_ANEG 0x0008 /* Autonegotiation capable */ |
81 | #define BMSR_LINK 0x0004 /* Link status */ |
82 | #define BMSR_JABBER 0x0002 /* Jabber detected */ |
83 | #define BMSR_EXTCAP 0x0001 /* Extended capability */ |
84 | |
85 | /* |
86 | * Note that the EXTSTAT bit indicates that there is extended status |
87 | * info available in register 15, but 802.3 section 22.2.4.3 also |
88 | * states that all 1000 Mb/s capable PHYs will set this bit to 1. |
89 | */ |
90 | |
91 | #define BMSR_MEDIAMASK (BMSR_100T4|BMSR_100TXFDX|BMSR_100TXHDX| \ |
92 | BMSR_10TFDX|BMSR_10THDX|BMSR_100T2FDX|BMSR_100T2HDX) |
93 | |
94 | /* |
95 | * Convert BMSR media capabilities to ANAR bits for autonegotiation. |
96 | * Note the shift chopps off the BMSR_ANEG bit. |
97 | */ |
98 | #define BMSR_MEDIA_TO_ANAR(x) (((x) & BMSR_MEDIAMASK) >> 6) |
99 | |
100 | #define MII_PHYIDR1 0x02 /* ID register 1 (ro) */ |
101 | |
102 | #define MII_PHYIDR2 0x03 /* ID register 2 (ro) */ |
103 | #define IDR2_OUILSB 0xfc00 /* OUI LSB */ |
104 | #define IDR2_MODEL 0x03f0 /* vendor model */ |
105 | #define IDR2_REV 0x000f /* vendor revision */ |
106 | |
107 | #define MII_ANAR 0x04 /* Autonegotiation advertisement (rw) */ |
108 | /* section 28.2.4.1 and 37.2.6.1 */ |
109 | #define ANAR_NP 0x8000 /* Next page (ro) */ |
110 | #define ANAR_ACK 0x4000 /* link partner abilities acknowledged (ro) */ |
111 | #define ANAR_RF 0x2000 /* remote fault (ro) */ |
112 | /* Annex 28B.2 */ |
113 | #define ANAR_FC 0x0400 /* local device supports PAUSE */ |
114 | #define ANAR_T4 0x0200 /* local device supports 100bT4 */ |
115 | #define ANAR_TX_FD 0x0100 /* local device supports 100bTx FD */ |
116 | #define ANAR_TX 0x0080 /* local device supports 100bTx */ |
117 | #define ANAR_10_FD 0x0040 /* local device supports 10bT FD */ |
118 | #define ANAR_10 0x0020 /* local device supports 10bT */ |
119 | #define ANAR_CSMA 0x0001 /* protocol selector CSMA/CD */ |
120 | #define ANAR_PAUSE_NONE (0 << 10) |
121 | #define ANAR_PAUSE_SYM (1 << 10) |
122 | #define ANAR_PAUSE_ASYM (2 << 10) |
123 | #define ANAR_PAUSE_TOWARDS (3 << 10) |
124 | |
125 | /* Annex 28D */ |
126 | #define ANAR_X_FD 0x0020 /* local device supports 1000BASE-X FD */ |
127 | #define ANAR_X_HD 0x0040 /* local device supports 1000BASE-X HD */ |
128 | #define ANAR_X_PAUSE_NONE (0 << 7) |
129 | #define ANAR_X_PAUSE_SYM (1 << 7) |
130 | #define ANAR_X_PAUSE_ASYM (2 << 7) |
131 | #define ANAR_X_PAUSE_TOWARDS (3 << 7) |
132 | |
133 | #define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */ |
134 | /* section 28.2.4.1 and 37.2.6.1 */ |
135 | #define ANLPAR_NP 0x8000 /* Next page (ro) */ |
136 | #define ANLPAR_ACK 0x4000 /* link partner accepted ACK (ro) */ |
137 | #define ANLPAR_RF 0x2000 /* remote fault (ro) */ |
138 | #define ANLPAR_FC 0x0400 /* link partner supports PAUSE */ |
139 | #define ANLPAR_T4 0x0200 /* link partner supports 100bT4 */ |
140 | #define ANLPAR_TX_FD 0x0100 /* link partner supports 100bTx FD */ |
141 | #define ANLPAR_TX 0x0080 /* link partner supports 100bTx */ |
142 | #define ANLPAR_10_FD 0x0040 /* link partner supports 10bT FD */ |
143 | #define ANLPAR_10 0x0020 /* link partner supports 10bT */ |
144 | #define ANLPAR_CSMA 0x0001 /* protocol selector CSMA/CD */ |
145 | #define ANLPAR_PAUSE_MASK (3 << 10) |
146 | #define ANLPAR_PAUSE_NONE (0 << 10) |
147 | #define ANLPAR_PAUSE_SYM (1 << 10) |
148 | #define ANLPAR_PAUSE_ASYM (2 << 10) |
149 | #define ANLPAR_PAUSE_TOWARDS (3 << 10) |
150 | |
151 | #define ANLPAR_X_FD 0x0020 /* local device supports 1000BASE-X FD */ |
152 | #define ANLPAR_X_HD 0x0040 /* local device supports 1000BASE-X HD */ |
153 | #define ANLPAR_X_PAUSE_MASK (3 << 7) |
154 | #define ANLPAR_X_PAUSE_NONE (0 << 7) |
155 | #define ANLPAR_X_PAUSE_SYM (1 << 7) |
156 | #define ANLPAR_X_PAUSE_ASYM (2 << 7) |
157 | #define ANLPAR_X_PAUSE_TOWARDS (3 << 7) |
158 | |
159 | #define MII_ANER 0x06 /* Autonegotiation expansion (ro) */ |
160 | /* section 28.2.4.1 and 37.2.6.1 */ |
161 | #define ANER_MLF 0x0010 /* multiple link detection fault */ |
162 | #define ANER_LPNP 0x0008 /* link parter next page-able */ |
163 | #define ANER_NP 0x0004 /* next page-able */ |
164 | #define ANER_PAGE_RX 0x0002 /* Page received */ |
165 | #define ANER_LPAN 0x0001 /* link parter autoneg-able */ |
166 | |
167 | #define MII_ANNP 0x07 /* Autonegotiation next page */ |
168 | /* section 28.2.4.1 and 37.2.6.1 */ |
169 | |
170 | #define MII_ANLPRNP 0x08 /* Autonegotiation link partner rx next page */ |
171 | /* section 32.5.1 and 37.2.6.1 */ |
172 | |
173 | /* This is also the 1000baseT control register */ |
174 | #define MII_100T2CR 0x09 /* 100base-T2 control register */ |
175 | #define GTCR_TEST_MASK 0xe000 /* see 802.3ab ss. 40.6.1.1.2 */ |
176 | #define GTCR_MAN_MS 0x1000 /* enable manual master/slave control */ |
177 | #define GTCR_ADV_MS 0x0800 /* 1 = adv. master, 0 = adv. slave */ |
178 | #define GTCR_PORT_TYPE 0x0400 /* 1 = DCE, 0 = DTE (NIC) */ |
179 | #define GTCR_ADV_1000TFDX 0x0200 /* adv. 1000baseT FDX */ |
180 | #define GTCR_ADV_1000THDX 0x0100 /* adv. 1000baseT HDX */ |
181 | |
182 | /* This is also the 1000baseT status register */ |
183 | #define MII_100T2SR 0x0a /* 100base-T2 status register */ |
184 | #define GTSR_MAN_MS_FLT 0x8000 /* master/slave config fault */ |
185 | #define GTSR_MS_RES 0x4000 /* result: 1 = master, 0 = slave */ |
186 | #define GTSR_LRS 0x2000 /* local rx status, 1 = ok */ |
187 | #define GTSR_RRS 0x1000 /* remote rx status, 1 = ok */ |
188 | #define GTSR_LP_1000TFDX 0x0800 /* link partner 1000baseT FDX capable */ |
189 | #define GTSR_LP_1000THDX 0x0400 /* link partner 1000baseT HDX capable */ |
190 | #define GTSR_LP_ASM_DIR 0x0200 /* link partner asym. pause dir. capable */ |
191 | #define GTSR_IDLE_ERR 0x00ff /* IDLE error count */ |
192 | |
193 | #define MII_PSECR 0x0b /* PSE control register */ |
194 | #define PSECR_PACTLMASK 0x000c /* pair control mask */ |
195 | #define PSECR_PSEENMASK 0x0003 /* PSE enable mask */ |
196 | #define PSECR_PINOUTB 0x0008 /* PSE pinout Alternative B */ |
197 | #define PSECR_PINOUTA 0x0004 /* PSE pinout Alternative A */ |
198 | #define PSECR_FOPOWTST 0x0002 /* Force Power Test Mode */ |
199 | #define PSECR_PSEEN 0x0001 /* PSE Enabled */ |
200 | #define PSECR_PSEDIS 0x0000 /* PSE Disabled */ |
201 | |
202 | #define MII_PSESR 0x0c /* PSE status register */ |
203 | #define PSESR_PWRDENIED 0x1000 /* Power Denied */ |
204 | #define PSESR_VALSIG 0x0800 /* Valid PD signature detected */ |
205 | #define PSESR_INVALSIG 0x0400 /* Invalid PD signature detected */ |
206 | #define PSESR_SHORTCIRC 0x0200 /* Short circuit condition detected */ |
207 | #define PSESR_OVERLOAD 0x0100 /* Overload condition detected */ |
208 | #define PSESR_MPSABSENT 0x0080 /* MPS absent condition detected */ |
209 | #define PSESR_PDCLMASK 0x0070 /* PD Class mask */ |
210 | #define PSESR_STATMASK 0x000e /* PSE Status mask */ |
211 | #define PSESR_PAIRCTABL 0x0001 /* PAIR Control Ability */ |
212 | #define PSESR_PDCL_4 (4 << 4) /* Class 4 */ |
213 | #define PSESR_PDCL_3 (3 << 4) /* Class 3 */ |
214 | #define PSESR_PDCL_2 (2 << 4) /* Class 2 */ |
215 | #define PSESR_PDCL_1 (1 << 4) /* Class 1 */ |
216 | #define PSESR_PDCL_0 (0 << 4) /* Class 0 */ |
217 | |
218 | #define MII_MMDACR 0x0d /* MMD access control register */ |
219 | #define MMDACR_FUNCMASK 0xc000 /* function */ |
220 | #define MMDACR_DADDRMASK 0x001f /* device address */ |
221 | #define MMDACR_FN_ADDRESS (0 << 14) /* address */ |
222 | #define MMDACR_FN_DATANPI (1 << 14) /* data, no post increment */ |
223 | #define MMDACR_FN_DATAPIRW (2 << 14) /* data, post increment on r/w */ |
224 | #define MMDACR_FN_DATAPIW (3 << 14) /* data, post increment on wr only */ |
225 | |
226 | #define MII_MMDAADR 0x0e /* MMD access address data register */ |
227 | |
228 | #define MII_EXTSR 0x0f /* Extended status register */ |
229 | #define EXTSR_1000XFDX 0x8000 /* 1000X full-duplex capable */ |
230 | #define EXTSR_1000XHDX 0x4000 /* 1000X half-duplex capable */ |
231 | #define EXTSR_1000TFDX 0x2000 /* 1000T full-duplex capable */ |
232 | #define EXTSR_1000THDX 0x1000 /* 1000T half-duplex capable */ |
233 | |
234 | #define EXTSR_MEDIAMASK (EXTSR_1000XFDX|EXTSR_1000XHDX| \ |
235 | EXTSR_1000TFDX|EXTSR_1000THDX) |
236 | |
237 | #endif /* _DEV_MII_MII_H_ */ |
238 | |